SELSE – Silicon Errors in Logic – System Effects
27-28 March 2019, Stanford, California, USA
Paper Submission Extended to January 21, 2019
The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, especially in safety-critical aerospace and automotive applications. The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also solicited.
We are happy to announce that top SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the problem being addressed, technical contributions, quality of results, and authors’ agreement to travel to present at DSN 2019, which will be held in Portland, Oregon.
Areas of Interest: Key areas of interest include (but are not limited to):
- Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
- New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
- Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
- Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
- Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
- The design of resilient systems for space exploration.
- The interplay between system security issues and reliability.
- Paper Registration (mandatory): January 14, 2019
January 7, 2019
- Paper Submission (for registered papers): January 21, 2019
January 18, 2019
- Author Notification: February 15, 2019
- Early Workshop Registration: February 22, 2019
- Camera-Ready Submission: March 8, 2019
Front picture is by John Daly.