SELSE – Silicon Errors in Logic – System Effects

SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects

27-28 March 2019, Stanford, California, USA

 

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, especially in safety-critical aerospace and automotive applications. The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also solicited.

We are happy to announce that top SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the problem being addressed, technical contributions, quality of results, and authors’ agreement to travel to present at DSN 2019, which will be held in Portland, Oregon.

Key areas of interest are (but not limited to):

  • Technology trends and their impact on error rates including experimental data on failures and characterization of reliability of systems deployed in the field and mitigation of issues.
  • New error mitigation techniques and error handling protocols for robust system design.
  • Case studies describing the tradeoff analysis for reliable systems including characterizing the overhead and design complexity of error mitigation techniques.
  • System-level error models.
  • Software-level impact of hardware failures software frameworks for resilience.
  • Impact of machine learning components on system resilience.
  • Resilience in new architectures including accelerator-rich systems and inexact or approximate computing.
  • (New) System security issues that impact and interact with system reliability.
 

Important dates:

  • Paper Registration (mandatory):    December 19, 2018
  • Paper Submission:                        January 11, 2019
  • Author Notification:                       February 15, 2019
  • Camera-Ready Submission:           March 1, 2019

Front picture is “Taken at Stanford University” By Mountain  CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=22526177

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