Call for Papers

The 14th IEEE Workshop on Silicon Errors in Logic – System Effects
SELSE 2018 (

April 3 – April 4, 2018 – Boston, Massachusetts, USA

 Important dates:

  • Abstract Submission (Mandatory): January 12, 2018 (December 20, 2017)
  • Paper Submission (For Registered Abstracts) : January 19, 2018 (January 12, 2018)
  • Author Notification: February 19, 2018
  • Camera-Ready Submission: March 1, 2018

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design and failures in memories account for a significant fraction of costly product returns. Emerging logic and memory device technologies introduce several reliability challenges that need to be addressed to make these technologies viable. Additionally, reliability is a key issue for large-scale systems, such as those in data centers and cloud computing infrastructure.

The SELSE workshop provides a forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):

  • Technology trends and their impact on error rates.
  • New error mitigation techniques.
  • Error handling protocols (higher-level protocols for robust system design).
  • Characterizing the overhead and design complexity of error mitigation techniques.
  • Case studies describing the tradeoff analysis for reliable systems.
  • System-level models: derating factors and validation of error models.
  • Experimental data on failures in current and emerging technologies
  • Characterization of reliability of systems deployed in the field and mitigation of issues.
  • Software-level impact of hardware failures.
  • Software frameworks for resilience.
  • Impact of machine learning components on system resilience.
  • Resilient accelerator-rich systems.


The full paper submission deadline is Januray 19, 2018 (absolutely no extensions). Papers will be considered for both oral and poster presentation, and all accepted submissions will be distributed to SELSE participants. Authors will be notified by Febrary 19, 2018. Final papers are due on March 1, 2018. All times 11:59pm CST.

Additional information and guidelines for submission are available at Submissions and final papers should be in PDF following IEEE two-column transactions format that does not exceed six printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE.