Call for Papers

The 15th IEEE Workshop on Silicon Errors in Logic – System Effects
SELSE 2019 (http://www.selse.org)

March 27 – March 28, 2019, Stanford, California, USA

 

Important dates:

Paper Registration (mandatory):       December 19, 2018

 

  • Paper Submission (for registered papers):      January 11, 2019
  • Author Notification:       February 15, 2019
  • Camera-Ready Submission:       March 1, 2019

 

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, especially in safety-critical aerospace and automotive applications. The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also solicited.

We are happy to announce that top SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2019. These papers will be selected based on the importance of the problem being addressed, technical contributions, quality of results, and authors’ agreement to travel to present at DSN 2019, which will be held in Portland, Oregon.

 

Areas

Key areas of interest are (but not limited to):

  • Technology trends and their impact on error rates including experimental data on failures and characterization of reliability of systems deployed in the field and mitigation of issues.
  • New error mitigation techniques and error handling protocols for robust system design.
  • Case studies describing the tradeoff analysis for reliable systems including characterizing the overhead and design complexity of error mitigation techniques.
  • System-level error models.
  • Software-level impact of hardware failures software frameworks for resilience.
  • Impact of machine learning components on system resilience.
  • Resilience in new architectures including accelerator-rich systems and inexact or approximate computing.
  • (New) System security issues that impact and interact with system reliability.

 

Submission Guidelines

Additional information and guidelines for submission are available at http://www.selse.org.  Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries—however, they are distributed to attendees of the workshop. Authors have the option of making their presentation slides available on the SELSE website, but this is not mandatory.

 

Organizing Committee

 

General Co-Chairs Laura Monroe, LANL
John Daly, LPS
Program Co-Chairs MIchael Sullivan, NVIDIA

Puneet Gupta, UCLA

(Emeritus) Paolo Rech, UFRGS
Finance Co-Chairs Steven Raasch, AMD

Sarah MIchalak, LANL

Publicity Co-Chairs Michael Sullivan, NVIDIA

Tiago Balen, UFRGS

Stefano Di Carlo, PoliTo

Yi-Pin Fang, TSMC

Documents Chair TBD
Bay Area Industry Liaison TBD
Webmaster Vanessa Job, LANL/UNM
Local Arrangements Chair Saurabh Hukerikar, NVIDIA
Advisors to the Committee Sarah Michalak, LANL

Alan Wood, Oracle

Vilas Sridharan, AMD